Systematic Testbench Specification for Constrained Randomized Test and Functional Coverage

Functional Verification is well-accepted for Electronic System Level (ESL) based designs and is supported by a variety of standardized Hardware Verification Languages like PSL, e, and SystemVerilog. In this article, we present the classification tree method for functional verification (CTM/FV) as a novel method to close the gap from the verification plan to the specification of randomized tests and functional coverage for test configurations. CTM/FV is introduced based on graphical means from which we automatically generate SystemVerilog code as a testbench for constraint-based randomized tests and functional coverage, where concepts are outlined by the automotive example of an adaptive cruise controller.